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SSTU32865
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications
Rev. 02 -- 28 September 2004 Product data sheet
1. General description
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTU32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active-LOW). The SSTU32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which--while requiring a minimum 9 mm x 13 mm of board space--allows for adequate signal routing and escape using conventional card technology.
2. Features
s 28-bit data register supporting DDR2 s Fully compliant to JEDEC standard JESD82-9 s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (i.e. 2 x SSTU32864 or 2 x SSTU32866) s Parity checking function across 22 input data bits s Parity out signal s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switching) s Supports up to 450 MHz clock frequency of operation s Optimized pinout for high-density DDR2 module design s Chip-selects minimize power consumption by gating data outputs from changing state s Supports Stub Series Terminated Logic SSTL_18 data inputs s Differential clock (CK and CK) inputs s Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs s Single 1.8 V supply operation s Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
3. Applications
s High-density (e.g. 2 rank by 4) DDR2 registered DIMMs s DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1: Ordering information Solder process Package Name SSTU32865ET/G SSTU32865ET Pb-free (SnAgCu solder ball TFBGA160 compound) SnPb solder ball compound TFBGA160 Description Version plastic thin fine-pitch ball grid array package; SOT802-1 160 balls; body 9 x 13 x 0.8 mm plastic thin fine-pitch ball grid array package; SOT802-1 160 balls; body 9 x 13 x 0.8 mm Type number
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Product data sheet
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Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
5. Functional diagram
(CS ACTIVE) VREF DQ
22
PARIN
R
PARITY GENERATOR AND CHECKER
SSTU32865
PTYERR
Q0A D0 DQ Q0B R Q21A D21 DQ Q21B R QCS0A DQ R CSGATEEN DCS1 QCS1A DQ QCS1B R DCKE0, DCKE1 QCKE0A, QCKE1A QCKE0B, QCKE1B QODT0A, QODT1A QODT0B, QODT1B QCS0B
DCS0
2
DQ R
2
DODT0, DODT1
2
DQ R
2
RESET CK CK
002aaa386
Fig 1. Functional diagram of SSTU32865
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SSTU32865
1.8 V DDR registered buffer with parity
6. Pinning information
6.1 Pinning
SSTU32865ET/G SSTU32865ET
2 1 A B C D E F G H J K L M N P R T U V
002aab010
ball A1 index area
4 3 5
6 7
8 9
10 12 11
Transparent top view
Fig 2. Pin configuration for TFBGA160
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SSTU32865
1.8 V DDR registered buffer with parity
1 A B C D E F G H J K L M N P R T U V VREF D1 D3 D6 D7 D11 D18 CSGATEEN CK CK RESET D0 D17 D19 D13 DODT1 DCKE0 VREF
2 n.c. D2 D4 D5 D8 D9 D12 D15 DCS0 DCS1 D14 D10 D16 D21 D20 DODT0 DCKE1 m.c.l.
3 PARIN n.c.
4 n.c. n.c.
5 n.c. n.c.
6 QCKE1A QCKE1B
7 QCKE0A QCKE0B
8 Q21A Q21B
9 Q19A Q19B
10 Q18A Q18B
11 Q17B QODT0B QODT1B
12 Q17A QODT0A QODT1A Q20A Q16A Q1A Q2A Q5A QCS0A QCS1A Q6A Q10A Q9A Q11A Q15A Q14A Q8B Q8A
002aab011
VDDL VDDL VDDL VDDL VDDL GND VDDL GND GND VDDL GND GND
GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL
n.c. VDDL
n.c. VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND
Q20B Q16B Q1B Q2B Q5B QCS0B QCS1B Q6B Q10B Q9B Q11B Q15B Q14B
VDDL VDDL
VDDR GND
VDDR GND
m.c.l. m.c.l.
PTYERR n.c.
m.c.h. m.c.h.
Q3B Q3A
Q12B Q12A
Q7B Q7A
Q4B Q4A
Q13B Q13A
Q0B Q0A
160-ball, 12 x 18 grid; top view. An empty cell indicates no ball is populated at that grid point. n.c. denotes a no-connect (ball present but not connected to the die). m.c.l. denotes a pin that must be connected LOW. m.c.h. denotes a pin that must be connected HIGH.
Fig 3. Ball mapping
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SSTU32865
1.8 V DDR registered buffer with parity
6.2 Pin description
Table 2: Symbol Ungated inputs DCKE0, DCKE1 DODT0, DODT1 D0 to D21 U1, U2 T2, T1 M1, B1, B2, C1, C2, D2, D1, SSTL_18 E1, E2, F2, M2, F1, G2, R1, L2, H2, N2, N1, G1, P1, R2, P2 J2, K2 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. SSTL_18 DRAM function pins not associated with Chip Select. Pin description Pin Type Description
Chip Select gated inputs
Chip Select inputs DCS0, DCS1 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGATEEN = HIGH) when at least one Chip Select input is LOW. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.
Re-driven outputs Q0A to Q21A V11, F12, G12, V6, V9, H12, SSTL_18 L12, V8, V12, N12, M12, P12, V7, V10, T12, R12, E12, A12, A10, A9, D12, A8 U11, F11, G11, U6, U9, H11, L11, U8, U12, N11, M11, P11, U7, U10, T11, R11, E11, A11, B10, B9, D11, B8 J12, K12, J11, K11 A7, A6, B7, B6
Q0B to Q21B
QCS0A, QDS1A, QCS0B, QCS1B QCKE0A, QCKE1A, QCKE0B, QCKE1B
QODT0A, QODT1A, B12, C12, B11, C11 QODT0B, QODT1B Parity input PARIN Parity error PTYERR U4 open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). Chip Select Gate Enable. When HIGH, the D0 to D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0 to D21 inputs will be latched and redriven on every rising edge of the clock.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
A3
SSTL_18
Parity input for the D0 to D21 inputs. Arrives one clock cycle after the corresponding data input.
Program inputs CSGATEEN H1 1.8 V LVCMOS
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SSTU32865
1.8 V DDR registered buffer with parity
Table 2: Symbol
Pin description ...continued Pin J1, K1 Type SSTL_18 Description Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Must be connected to a logic LOW Must be connected to a logic HIGH. 1.8 V LVCMOS 0.9 V nominal Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. power supply voltage power supply voltage ground
Clock inputs CK, CK
Miscellaneous inputs m.c.l. m.c.h. RESET U3, V2, V3 U5, V5 L1
VREF VDDL VDDR GND
A1, V1 D4, E4, E6, F4, G4, H4, K4, K5, N4, N5, P5, P6, R5, R6 E7, F8, F9, G8, G9, J8, J9, L8, L9, N8, N9, P7, P8 D5, D8, D9, E5, E8, E9, F5, G5, H5, H8, H9, J4, J5, K8, K9, L4, L5, M4, M5, M8, M9, P4, P9, R4, R7, R8, R9 A2, A4, A5, B3, B4, B5, D6, D7, V4
n.c.
ball present but not connected to die
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SSTU32865
1.8 V DDR registered buffer with parity
7. Functional description
7.1 Function table
Table 3: RESET H H H H H H H H H H H H H H H L Function table (each flip-flop) Inputs DCS0 L L L L L L H H H H H H H H H X or floating DCS1 L L L H H H L L L H H H H H H X or floating CSGATEEN X X X X X X X X X L L L H H H X or floating CK L or H L or H L or H L or H L or H X or floating CK L or H L or H L or H L or H L or H X or floating Dn, DODTn, DCKEn L H X L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs [1] QCS0 L L Q0 L L Q0 H H Q0 H H Q0 H H Q0 L QCS1 L L Q0 H H Q0 L L Q0 H H Q0 H H Q0 L QODTn, QCKEn L H Q0 L H Q0 L H Q0 L H Q0 L H Q0 L
[1]
Q0 is the previous state of the associated output.
Table 4: RESET H H H H H H H H H H L
[1]
Parity and standby function table Inputs DCS0 L L L L H H H H H X X or floating DCS1 H H H H L L L L H X X or floating CK L or H X or floating CK L or H X or floating of inputs = H (D0 to D21) even odd even odd even odd even odd X X X or floating PARIN [1] L L H H L L H H X X X or floating Output PTYERR [2] [3] H L L H H L L H PTYERR0 PTYERR0 H
PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated correctly.
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SSTU32865
1.8 V DDR registered buffer with parity
[2]
This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is `don't care' for PTYERR. PTYERR0 is the previous state of output PTYERR.
[3]
7.2 Functional information
This 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTU32865 ensures that the outputs remain LOW, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to ground, in which case, the setup-time requirement for DCSn would be the same as for the other Dn data inputs. The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
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SSTU32865
1.8 V DDR registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTU32865 for its basic register functionality, signal definition and performance is based upon the industry-standard SSTU32864, but provides key operational features which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the clock. The 22 `Chip-Select-gated' input signals associated with this function include addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they are independent of CS. The CS gating function can be disabled by tying CSGATEEN LOW, enabling all internal latches to be updated on every rising edge of the clock.
Table 5: Mode Gating Non-gating Chip Select gating mode Signal name CSGATEEN HIGH CSGATEEN LOW Description Registers only re-drive signals to the DRAMs when Chip Select inputs are LOW. Registers always re-drive signals on every clock cycle, independent of the state of the Chip Select inputs.
7.3.2 Parity error checking and reporting
The SSTU32865 incorporates a parity function, whereby the signal received on input pin PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs. The received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. The 22 CS-gated input signals will be latched and re-driven on the first clock, and any error will be reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a common signal pin for reporting the occurrence of a parity error during a valid command cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive clock cycles to allow the memory controller sufficient time to sense and capture the error even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all internal latches and all outputs will be driven LOW quickly except the PTYERR output, which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequence
The reset function for the SSTU32865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles.
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SSTU32865
1.8 V DDR registered buffer with parity
RESET
DCSn
m CK
m+1
m+2
m+3
m+4
CK tACT Dn (1) tPDM, tPDMSS CK to Q Qn
tsu
th
tsu PARIN tPHL CK to PTYERR PTYERR
th
tPHL, tPLH CK to PTYERR
002aaa983
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of tACT(max) to avoid false error.
Fig 4. RESET switches from LOW to HIGH
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SSTU32865
1.8 V DDR registered buffer with parity
RESET
DCSn
m CK
m+1
m+2
m+3
m+4
CK tsu th
Dn (1) tPDM, tPDMSS CK to Q Qn tsu
th
PARIN tPHL, tPLH CK to PTYERR PTYERR
Unknown input event
Output signal is dependent on the prior unknown event
002aaa984
HIGH or LOW
Fig 5. RESET being held HIGH
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SSTU32865
1.8 V DDR registered buffer with parity
RESET
tINACT
DCSn
CK (1)
CK (1)
Dn (1) tRPHL RESET to Q Qn
PARIN (1) tRPLH RESET to PTYERR PTYERR
002aaa985
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT(max).
Fig 6. RESET switches from HIGH to LOW
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SSTU32865
1.8 V DDR registered buffer with parity
Dn
22
DQ
22
QnA
QnB
D
D
LATCHING AND RESET FUNCTION(1)
PTYERR
PARIN
D
CLOCK
002aaa417
(1) This function holds the error for two cycles. For details, see Section 7 "Functional description" and Figure 4 "RESET switches from LOW to HIGH".
Fig 7. Parity logic diagram
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1.8 V DDR registered buffer with parity
8. Limiting values
Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO ICCC Tstg Vesd Parameter supply voltage receiver input voltage driver output voltage input clamp current output clamp current continuous output current continuous current through each VDD or GND pin storage temperature electrostatic discharge voltage Human Body Model (HBM); 1.5 k; 100 pF Machine Model (MM); 0 ; 200 pF
[1]
[2] [2]
Conditions
Min -0.5 -0.5 -0.5 -65 2 200
Max +2.5 +2.5 VDD + 0.5 -50 50 50 100 +150 -
Unit V V V mA mA mA mA C kV V
VI < 0 V or VI > VDD VO < 0 V or VO > VDD 0 V < VO < VDD
Stresses beyond those listed under `absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under `recommended operating conditions' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
9. Recommended operating conditions
Table 7: Symbol VDD VREF VTT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb Recommended operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage common mode input voltage range differential input voltage HIGH-level output current LOW-level output current operating ambient temperature in free air data inputs (Dn) data inputs (Dn) data inputs (Dn) data inputs (Dn) RESET RESET CK, CK CK, CK
[1] [1] [1] [1] [2] [2]
Conditions
Min 1.7 0.49 x VDD VREF - 40 mV 0 VREF + 250 mV VREF + 125 mV 0.65 x VDD 0.675 600 0
Typ 0.50 x VDD VREF -
Max 1.9 0.51 x VDD VREF + 40 mV VDD VREF - 250 mV VREF - 125 mV 0.35 x VDD 1.125 -8 8 +70
Unit V V V V V V V V V V V mV mA mA C
[1] [2]
The differential inputs must not be floating, unless RESET is LOW. The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
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SSTU32865
1.8 V DDR registered buffer with parity
10. Characteristics
Table 8: Characteristics Over recommended operating conditions, unless otherwise noted. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current static standby current static operating current IDDD Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 1.9 V RESET = GND; VDD = 1.9 V RESET = VDD; VDD = 1.9 V; VI = VIH(AC) or VIL(AC) Min 1.2 Typ 16 Max 0.5 5 100 40 Unit V V A A mA A
dynamic operating current per MHz, RESET = VDD; clock only VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V dynamic operating current per MHz, RESET = VDD; per each data input VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V
-
19
-
A
Ci
input capacitance, data inputs input capacitance, CK and CK input capacitance, RESET
VI = VREF 250 mV; VDD = 1.8 V VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V VI = VDD or GND; VDD = 1.8 V
2.5 2 3
-
3.5 3 5
pF pF pF
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SSTU32865
1.8 V DDR registered buffer with parity
Table 9: Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol fclock tW tACT tINACT tsu Parameter clock frequency pulse duration, CK, CK HIGH or LOW differential inputs active time differential inputs inactive time setup time, Chip Select setup time, Data setup time, PARIN th hold time hold time, PARIN
[1] [2] [3] This parameter is not necessarily production tested. Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
[1] [2] [1] [3]
Conditions
Min 1 0.7 0.5 0.5 0.5 0.5
Typ -
Max 450 10 15 -
Unit MHz ns ns ns ns ns ns ns ns
DCS0, DCS1 valid before clock switching Dn valid before clock switching PARIN before CK and CK input to remain valid after clock switching PARIN after CK and CK
Table 10: Switching characteristics Over recommended operating conditions, unless otherwise noted. Symbol fMAX tPDM tLH tHL tPLH tPDMSS tPHL
[1] [2]
Parameter maximum input clock frequency propagation delay LOW-to-HIGH delay HIGH-to-LOW delay LOW-to-HIGH propagation delay propagation delay, simultaneous switching propagation delay
Conditions CK and CK to output CK and CK to PTYERR CK and CK to PTYERR from RESET to PTYERR CK and CK to output RESET to output
[1] [2] [1]
Min 450 1.41 1.2 1 -
Typ -
Max 1.8 3 3 3 2.0 3
Unit MHz ns ns ns ns ns ns
Includes 350 ps of test-load transmission line delay. This parameter is not necessarily production tested.
Table 11: Output edge rates Over recommended operating conditions, unless otherwise noted. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate absolute difference between dV/dt_r and dV/dt_f Conditions Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
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1.8 V DDR registered buffer with parity
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT TL = 50 CK inputs CK CK test point
RL = 100
TL = 350 ps, 50 OUT
CL = 30 pF(1)
RL = 1000
RL = 1000
002aaa371
test point
(1) CL includes probe and jig capacitance.
Fig 8. Load circuit
LVCMOS VDD RESET VDD/2 tINACT IDD(1) VDD/2 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 9. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 10. Voltage waveforms; pulse duration
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Product data sheet
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SSTU32865
1.8 V DDR registered buffer with parity
CK VICR CK tsu input VREF th VIH VREF VIL
002aaa374
VID
VID = 600 mV VREF = VDD/2 VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; setup and hold times
CK VICR CK tPLH tPHL VOH output VTT
002aaa375
VICR
Vi(p-p)
VOL
tPLH and tPHL are the same as tPD.
Fig 12. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET VDD/2 VIL tPHL VOH output VTT
002aaa376
VOL
tPLH and tPHL are the same as tPD. VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; propagation delay times (reset to output)
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Product data sheet
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SSTU32865
1.8 V DDR registered buffer with parity
11.2 Output slew rate measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement
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Product data sheet
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SSTU32865
1.8 V DDR registered buffer with parity
11.3 Error output load circuit and voltage measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 1 k
OUT
CL = 10 pF(1)
test point
002aaa500
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, error output measurements
LVCMOS RESET VCC/2
VCC
0V tPLH VOH 0.15 V
002aaa501
output waveform 2
0V
Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input
timing inputs
VICR tHL
VICR
Vi(p-p)
VCC output waveform 1 VCC/2
002aaa502
VOL
Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
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Product data sheet
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Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
timing inputs
VICR tLH
VICR
Vi(p-p)
VOH output waveform 2 0.15 V
002aaa503
0V
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
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Product data sheet
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SSTU32865
1.8 V DDR registered buffer with parity
12. Package outline
TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.8 mm SOT802-1
D
B
A
ball A1 index area E A2 A1
A
detail X
e1 e b 1/2e
V U T R P N M L K J H G F E D C B A
C
v M C A B w M C
y1 C
y
e
e2 1/2e
ball A1 index area
1
2
3
4
5
6
7
8
9
10
11
12
X 0 5 scale 10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.35 0.25 A2 0.85 0.75 b 0.45 0.35 D 9.1 8.9 E 13.1 12.9 e 0.65 e1 7.15 e2 11.05 v 0.15 w 0.08 y 0.1 y1 0.1
OUTLINE VERSION SOT802-1
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 03-01-29
Fig 22. Package outline SOT802-1 (TFBGA160)
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Product data sheet
Rev. 02 -- 28 September 2004
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SSTU32865
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13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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SSTU32865
1.8 V DDR registered buffer with parity
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
13.5 Package related soldering information
Table 12: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
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Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
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Product data sheet
Rev. 02 -- 28 September 2004
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Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
14. Revision history
Table 13: Revision history Release date 20040928 Data sheet status Product data sheet Change notice Doc. number 9397 750 13799 Supersedes SSTU32865-01 Document ID SSTU32865_2 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 1 "General description": acronym TFBGA defined. Section 2 "Features": acronym SSTL defined. Additional features added to Section 2 "Features" Section 6 "Pinning information" - change `MCL' to `m.c.l.' and `MCH' to `m.c.h.' - add descriptions for VDDL and VDDR in Table 2 "Pin description" - added Figure 2 "Pin configuration for TFBGA160" - added Figure 3 "Ball mapping" (replaces Table 2 "Ball mapping")
* * *
Table 3 "Function table (each flip-flop)" and Table 4 "Parity and standby function table" moved to Section 7.1 on page 8. Table 3 "Function table (each flip-flop)": add Table note 1 and its reference at `Outputs'. Table 4 "Parity and standby function table": - Table note 2: change `This transition assumes ...' to `This condition assumes ...'. - Add Table note 3.
* *
Section 7.3.4 "Power-up sequence": add `(HIGH)' after `... and will be held clear'. Table 6 "Limiting values": - Symbol Vi changed to VI; Symbol Vo changed to VO. - Symbols ESDHBM and ESDMM replaced with Vesd (added model types under "Conditions")
*
Table 7 "Recommended operating conditions": - change VIH (for data inputs) to VIH(AC) and VIH(DC); condition changed to `data inputs (Dn)' - change VIL (for data inputs) to VIL(AC) and VIL(DC); condition changed to `data inputs (Dn) - Table note split into 2 notes; references added.
*
Table 8 "Characteristics" - change IDDD Parameter from "dynamic operating current ..." to "dynamic operating current per MHz ..."; change Unit from "A/MHz" to "A". - change Typical value for IDDD (clock only) from TBD to 16 A - change Typical value for IDDD (per each data input) from TBD to 19 A
*
Table 9 "Timing requirements": - change symbol fCLOCK to fclock - change fclock maximum value from 270 MHz to 450 MHz - change symbol tSU to tsu; under `Conditions', change `Chip Select' to `DCS0, DCS1'. - change symbol tH to th
*
Table 10 "Switching characteristics": - change fMAX minimum value from 270 MHz to 450 MHz - change tPDM maximum value from 2.15 ns to 1.8 ns - change tPDMSS maximum value from 2.35 ns to 2.0 ns
*
SSTU32865-01
Section 11.1 "Test circuit": acronym PRR defined; titles for Figure 12 and Figure 13 modified. Product data 9397 750 10942 -
20040705
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Product data sheet
Rev. 02 -- 28 September 2004
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Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
Rev. 02 -- 28 September 2004
28 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 8 9 10 11 11.1 11.2 11.3 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 8 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional information . . . . . . . . . . . . . . . . . . . 9 Functional differences to SSTU32864 . . . . . . 10 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN). . . . . . . . . . . . . . 10 Parity error checking and reporting. . . . . . . . . 10 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up sequence . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended operating conditions. . . . . . . 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output slew rate measurement. . . . . . . . . . . . 20 Error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25 Package related soldering information . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Contact information . . . . . . . . . . . . . . . . . . . . 28
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 28 September 2004 Document number: 9397 750 13799
Published in the U.S.A.

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